The present disclosure relates generally to memory subsystems of computer systems and more specifically to systems, devices, and methods for improving the performance and the memory capacity of memory subsystems or memory “boards,” particularly memory boards that include dual in-line memory modules (DIMMs).
Certain types of computer memory subsystems include a plurality of dynamic random-access memory (DRAM) or synchronous dynamic random access memory (SDRAM) devices mounted on a printed circuit board (PCB). These memory subsystems or memory “boards” are typically mounted in a memory slot or socket of a computer system, such as a server system or a personal computer, and are accessed by the processor of the computer system. Memory boards typically include one or more memory modules, each with a plurality of memory devices (such as DRAMs or SDRAMs) in a unique configuration of rows, columns, and banks, which provide in a total memory capacity for the memory module.
The memory devices of a memory module are generally arranged as ranks or rows of memory, each rank of memory generally having a bit width. For example, a memory module in which each rank of the memory module is 64 bits wide is described as having an “x64” or “by 64” organization. Similarly, a memory module having 72-bit-wide ranks is described as having an “x72” or “by 72” organization.
The memory capacity of a memory module increases with the number of memory devices. The number of memory devices of a memory module can be increased by increasing the number of memory devices per rank or by increasing the number of ranks. Rather than referring to the memory capacity of the memory module, in certain circumstances, the memory density of the memory module is referred to instead.
During operation, the ranks of a memory module are selected or activated by control signals that are received from the processor. Examples of such control signals include, but are not limited to, rank-select signals, also called chip-select signals. Most computer and server systems support a limited number of ranks per memory module, which limits the memory density that can be incorporated in each memory module.
The memory space in an electronic system is limited by the physically addressable space that is defined by the number of address bits, or by the number of chips selected. In general, once the memory space is defined for an electronic system, it would not be feasible to modify the memory space without an extensive design change. This is especially true for the case in which a memory space is defined by a consortium, such as JEDEC. A problem arises when a user's application requires a larger addressable memory space than the memory space that the current electronic system is designed to support.
In developing a memory subsystem, consideration is always given to memory density, power dissipation (or thermal dissipation), speed, and cost. Generally, these attributes are not orthogonal to each other, meaning that optimizing one attribute may detrimentally affect another attribute. For example, increasing memory density typically causes higher power dissipation, slower operational speed, and higher costs.
Furthermore, the specifications of the memory subsystem may be guided by physical limitations associated with these attributes. For example, high thermal dissipation may limit the speed of the operation, or the physical size of the memory module may limit the density of the module.
These attributes generally dictate the design parameters of the memory module usually requiring that the memory system slow down operation speed if the memory subsystem is populated with more memory devices to provide higher density memory cards.
Currently there are two major methods of increasing memory space. The first method is based on an address decoding scheme. This method is very widely adopted in the electronics industry in designing Application-Specific Integrated Circuit (ASIC) and System-On-Chip (SOC) devices to expand system memories. The second method increases the addressable memory space without extensive alteration of the software or hardware of an existing electronics system. This method combines chip select signals with an address signal to double the number of physically addressable memory spaces. These methods have several shortcomings. For example, since these methods increase the addressable memory space by directly adding memory chips, a heavier load is presented to the system controller outputs and the memory device outputs, resulting in a slower system. Also, increasing the number of memory devices also results in higher power dissipation. In addition, since an increase in the number of memory devices on each memory card alters the physical property of the memory card while the system board remains the same, the overall signal (transmission line) wave characteristics deviate from the original design intent or specification. Furthermore, especially when registered DIMMs (RDIMMs) are used, the increase in the number of the memory devices translates to an increase in the distributed RC load on the data paths, but not on the address and control paths, thereby introducing uneven signal propagation delay between the data signal paths and address and control signal paths.
FIGS. 1 and 2 illustrate the prior art approach of increasing the number of memory devices. Specifically, FIG. 1 shows a standard memory subsystem 100 with at least one JEDEC standard two-rank memory module 110 (e.g., a registered dual in-line memory module, or “RDIMM,” only one of which is shown for clarity), wherein each module comprises a plurality memory devices 112 (e.g., DRAMs or SDRAMs). This subsystem requires each data line of an array of data lines 150 from a system memory controller 120 to be connected to a memory device 112 in each rank in each memory module 110. A register 130 receive a plurality of address and control lines 140 from the controller 120. Therefore, the system memory controller 120 see all the memory devices 112 as its load during a write operation, and each memory device 112 also sees multiple other memory devices 112, as well as the system memory controller 120, as its load during a read operation. FIG. 2 is a schematic view of a standard memory subsystem 100′ with at least one JEDEC standard four-rank memory module 160 (only one of which is shown), each comprising a plurality of memory devices 162. Each memory module 160 presents four fanouts to the data outputs of the system memory controller 120′, which is connected to each of the memory devices by means of a register 130′ receiving a plurality of address and control lines 140′, and by means of an array of data lines 150′. Therefore, as with the two-rank module shown in FIG. 1, the system memory controller 120′ sees all the memory devices 162 as its load during a write operation, while each memory device 162 sees multiple other memory devices 162 and the system memory controller 120′ as its load during a read operation.
Therefore, these prior art techniques not only reduce the speed of the memory systems, but they also require hardware modifications to minimize any deviation of the transmission line wave characteristics from the original design specification